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import logging
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import struct
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import time
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from chirp import directory, bitwise, errors, chirp_common, memmap
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import thd72
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from chirp.util import hexprint
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LOG = logging.getLogger(__name__)
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# Save files from MCP-D74 have a 256-byte header, and possibly some oddness
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# TH-D74 memory map
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# 0x02000: memory flags, 4 bytes per memory
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# 0x04000: memories, each 40 bytes long
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# 0x10000: names, each 16 bytes long, null padded, ascii encoded
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# memory channel
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# 0 1 2 3 4 5 6 7 8 9 a b c d e f
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# [freq ] ? mode tmode/duplex rtone ctone dtcs cross_mode [offset] ?
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# frequency is 32-bit unsigned little-endian Hz
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# Some of the blocks written by MCP have a length set of less than 0x00/256
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BLOCK_SIZES = {
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0x0003: 0x00B4,
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0x0007: 0x0068,
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}
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mem_format = """
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// TODO: find lockout
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#seekto 0x02000;
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struct {
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// 4 bytes long
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u8 disabled;
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u8 unk;
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u8 group;
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u8 unk2;
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} flag[1000];
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#seekto 0x04000;
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// TODO: deal with the 16-byte trailers of every block
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struct {
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struct {
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ul32 freq;
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ul32 offset;
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u8 tuning_step:4,
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unk:4;
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u8 mode:4,
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unk1:4;
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u8 tone_mode:4,
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duplex:4;
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u8 rtone;
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u8 ctone;
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u8 dtcs;
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u8 cross_mode:4
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digital_squelch:4;
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char urcall[8];
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char rpt1[8];
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char rpt2[8];
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u8 digital_squelch_code;
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} mem[6];
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u8 pad[16];
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} memory[160]; // TODO: correct number of memories
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#seekto 0x10000;
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struct {
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char name[16];
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} channel_name[1000];
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"""
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STEPS = [5.0, 6.25, None, None, 10.0, 12.5, 15.0, 20.0, 25.0, 50.0, 100.0, 9.0]
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MODES = [
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"FM",
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"DV",
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"AM",
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"LSB",
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"USB",
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"CW",
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"NFM",
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"DV"
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]
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def hex(data):
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data_txt = ""
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for idx in range(0, len(data), 16):
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bytes = data[idx:idx+16].encode("hex").upper()
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for idx in range(0, len(bytes), 2):
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data_txt += bytes[idx:idx+2] + " "
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data_txt += "\n"
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return data_txt.strip()
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class SProxy(object):
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def __init__(self, delegate):
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self.delegate = delegate
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def read(self, len):
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r = self.delegate.read(len)
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LOG.debug("READ\n" + hex(r))
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return r
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def write(self, data):
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LOG.debug("WRITE\n" + hex(data))
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return self.delegate.write(data)
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@property
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def timeout(self):
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return self.delegate.timeout
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@timeout.setter
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def timeout(self, timeout):
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self.delegate.timeout = timeout
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@directory.register
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class THD74Radio(thd72.THD72Radio):
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MODEL = "TH-D74 (clone mode)"
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_memsize = 500480
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# I think baud rate might be ignored by USB-Serial stack of the D74's
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# on-board FTDI chip, but it doesn't seem to hurt.
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BAUD_RATE = 115200
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def __init__(self, pipe):
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pipe = SProxy(pipe)
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super(THD74Radio, self).__init__(pipe)
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def get_features(self):
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rf = super(THD74Radio, self).get_features()
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rf.has_tuning_step = True
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return rf
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def process_mmap(self):
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self._memobj = bitwise.parse(mem_format, self._mmap)
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self._dirty_blocks = []
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def sync_in(self):
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# self._detect_baud()
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self._mmap = self.download()
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self.process_mmap()
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def sync_out(self):
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if len(self._dirty_blocks):
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self.upload(self._dirty_blocks)
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else:
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self.upload()
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def read_block(self, block, count=256):
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cmd = struct.pack(">cHH", "R", block, count%256)
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self.pipe.write(cmd)
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r = self.pipe.read(5)
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if len(r) != 5:
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raise Exception("Did not receive block response")
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cmd, _block, _ = struct.unpack(">cHH", r)
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if cmd != "W" or _block != block:
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raise Exception("Invalid response: %s %i" % (cmd, _block))
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data = ""
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while len(data) < count:
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data += self.pipe.read(count - len(data))
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self.pipe.write(chr(0x06))
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if self.pipe.read(1) != chr(0x06):
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raise Exception("Did not receive post-block ACK!")
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return data
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def write_block(self, block, map, count=256):
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c = struct.pack(">cHH", "W", block, count%256)
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base = block * 256
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data = map[base:base + count]
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# It's crucial that these are written together. Otherwise the radio
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# will fail to ACK under some conditions.
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self.pipe.write(c + data)
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ack = self.pipe.read(1)
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return ack == chr(0x06)
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def _unlock(self):
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"""Voodoo sequence of operations to get the radio to accept our programming."""
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h = self.read_block(0, 6)
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c = struct.pack(">cHH", "W", 0, 0x30)
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self.pipe.write(c)
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# magic unlock sequence
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unlock = ("\xFF\x01\xFF\x00\x00\xFF\xFF\xFF\xFF\xFF\x01\xFF\xFF\xFF\x03\x01" +
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"\x00\x00\x00\x00\x02\x00\x30\x30\x30\x00\xFF\xFF\xFF\xFF\xFF\xFF" +
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"\xFF\x00\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF")
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self.pipe.write(unlock)
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ack = self.pipe.read(1)
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if ack != chr(0x06):
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raise errors.RadioError("Expected ack but got {} ({})".format(ord(ack), type(ack)))
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c = struct.pack(">cHH", "W", 0, 0x38C8)
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self.pipe.write(c)
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# magic unlock sequence
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unlock = [0xFF] * 8 + [0] * 160 + [0xFF] * 32
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unlock = "".join([chr(x) for x in unlock])
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self.pipe.write(unlock)
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time.sleep(0.01)
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ack = self.pipe.read(1)
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if ack != chr(0x06):
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raise errors.RadioError("Expected ack but got {} ({})".format(ord(ack), type(ack)))
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def download(self, raw=False, blocks=None):
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if blocks is None:
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blocks = range(self._memsize / 256)
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else:
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blocks = [b for b in blocks if b < self._memsize / 256]
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if self.command("0M PROGRAM", 2, timeout=1.5) != "0M":
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raise errors.RadioError("Radio didn't go into PROGRAM mode")
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allblocks = range(self._memsize / 256)
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self.pipe.baudrate = 57600
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try:
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self.pipe.setRTS()
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except AttributeError:
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self.pipe.rts = True
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self.pipe.read(1)
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data = ""
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LOG.debug("reading blocks %d..%d" % (blocks[0], blocks[-1]))
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total = len(blocks)
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count = 0
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for i in allblocks:
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if i not in blocks:
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data += 256 * '\xff'
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continue
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data += self.read_block(i)
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count += 1
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if self.status_fn:
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s = chirp_common.Status()
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s.msg = "Cloning from radio"
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s.max = total
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s.cur = count
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self.status_fn(s)
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self.pipe.write("E")
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if raw:
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return data
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return memmap.MemoryMap(data)
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def upload(self, blocks=None):
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# MCP-D74 sets DTR, so we should too
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try:
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self.pipe.setDTR()
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except AttributeError:
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self.pipe.dtr = True
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if blocks is None:
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blocks = range((self._memsize / 256) - 2)
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else:
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blocks = [b for b in blocks if b < self._memsize / 256]
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if self.command("0M PROGRAM", 2, timeout=1.5) != "0M":
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raise errors.RadioError("Radio didn't go into PROGRAM mode")
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if self._unlock():
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raise errors.RadioError("Unlock failed")
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# This block definitely isn't written conventionally, so we let _unlock
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# handle it and skip.
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blocks.remove(0)
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# For some reason MCP-D74 skips this block. If we don't, we'll get a NACK
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# on the next one.
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blocks.remove(1279)
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LOG.debug("writing blocks %d..%d" % (blocks[0], blocks[-1]))
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total = len(blocks)
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count = 0
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for i in blocks:
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time.sleep(0.001)
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r = self.write_block(i, self._mmap, BLOCK_SIZES.get(i, 256))
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count += 1
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if not r:
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raise errors.RadioError("write of block %i failed" % i)
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if self.status_fn:
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s = chirp_common.Status()
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s.msg = "Cloning to radio"
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s.max = total
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s.cur = count
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self.status_fn(s)
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self.pipe.write("F")
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# clear out blocks we uploaded from the dirty blocks list
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self._dirty_blocks = [b for b in self._dirty_blocks if b not in blocks]
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def command(self, cmd, response_length, timeout=0.5):
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start = time.time()
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LOG.debug("PC->D72: %s" % cmd)
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default_timeout = self.pipe.timeout
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self.pipe.write(cmd + "\r")
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self.pipe.timeout = timeout
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try:
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data = self.pipe.read(response_length + 1)
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LOG.debug("D72->PC: %s" % data.strip())
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finally:
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self.pipe.timeout = default_timeout
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return data.strip()
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def get_raw_memory(self, number):
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bank = number // 6
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idx = number % 6
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_mem = self._memobj.memory[bank].mem[idx]
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return repr(_mem) + \
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repr(self._memobj.flag[number])
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def get_id(self):
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r = self.command("ID", 9)
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if r.startswith("ID "):
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return r.split(" ")[1]
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else:
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raise errors.RadioError("No response to ID command")
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def get_memory(self, number):
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if isinstance(number, str):
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try:
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number = thd72.THD72_SPECIAL[number]
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except KeyError:
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raise errors.InvalidMemoryLocation("Unknown channel %s" %
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number)
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if number < 0 or number > (max(thd72.THD72_SPECIAL.values()) + 1):
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raise errors.InvalidMemoryLocation(
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"Number must be between 0 and 999")
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bank = number // 6
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idx = number % 6
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_mem = self._memobj.memory[bank].mem[idx]
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flag = self._memobj.flag[number]
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if MODES[_mem.mode] == "DV":
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mem = chirp_common.DVMemory()
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else:
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mem = chirp_common.Memory()
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mem.number = number
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if number > 999:
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mem.extd_number = thd72.THD72_SPECIAL_REV[number]
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if flag.disabled == 0xFF:
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mem.empty = True
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return mem
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mem.name = self.get_channel_name(number)
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mem.freq = int(_mem.freq)
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mem.tmode = thd72.TMODES[int(_mem.tone_mode)]
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mem.rtone = chirp_common.TONES[_mem.rtone]
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mem.ctone = chirp_common.TONES[_mem.ctone]
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mem.dtcs = chirp_common.DTCS_CODES[_mem.dtcs]
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mem.duplex = thd72.DUPLEX[int(_mem.duplex)]
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mem.offset = _mem.offset
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mem.mode = MODES[int(_mem.mode)]
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mem.tuning_step = STEPS[_mem.tuning_step]
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if mem.mode == "DV":
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mem.dv_urcall = _mem.urcall
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mem.dv_rpt1call = _mem.rpt1
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mem.dv_rpt2call = _mem.rpt2
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mem.dv_code = _mem.digital_squelch_code
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if number < 999:
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# mem.skip = chirp_common.SKIP_VALUES[int(flag.skip)]
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mem.cross_mode = chirp_common.CROSS_MODES[_mem.cross_mode]
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if number > 999:
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mem.cross_mode = chirp_common.CROSS_MODES[0]
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mem.immutable = ["number", "bank", "extd_number", "cross_mode"]
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if number >= 1020 and number < 1030:
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mem.immutable += ["freq", "offset", "tone", "mode",
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"tmode", "ctone", "skip"] # FIXME: ALL
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else:
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mem.immutable += ["name"]
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return mem
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def set_memory(self, mem):
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LOG.debug("set_memory(%d)" % mem.number)
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if mem.number < 0 or mem.number > (max(thd72.THD72_SPECIAL.values()) + 1):
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raise errors.InvalidMemoryLocation(
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"Number must be between 0 and 999")
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# weather channels can only change name, nothing else
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if mem.number >= 1020 and mem.number < 1030:
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self.set_channel_name(mem.number, mem.name)
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return
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flag = self._memobj.flag[mem.number]
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self.add_dirty_block(self._memobj.flag[mem.number])
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# only delete non-WX channels
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was_empty = flag.disabled == 0xf
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if mem.empty:
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flag.disabled = 0xf
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return
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flag.disabled = 0
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_mem = self._memobj.memory[mem.number]
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self.add_dirty_block(_mem)
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if was_empty:
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self.initialize(_mem)
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_mem.freq = mem.freq
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if mem.number < 999:
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self.set_channel_name(mem.number, mem.name)
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_mem.tone_mode = thd72.TMODES_REV[mem.tmode]
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_mem.rtone = chirp_common.TONES.index(mem.rtone)
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_mem.ctone = chirp_common.TONES.index(mem.ctone)
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_mem.dtcs = chirp_common.DTCS_CODES.index(mem.dtcs)
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_mem.cross_mode = chirp_common.CROSS_MODES.index(mem.cross_mode)
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_mem.duplex = thd72.DUPLEX_REV[mem.duplex]
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_mem.offset = mem.offset
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_mem.mode = thd72.MODES_REV[mem.mode]
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prog_vfo = thd72.get_prog_vfo(mem.freq)
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flag.prog_vfo = prog_vfo
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_mem.unknown1 = _mem.unknown2 = thd72.UNKNOWN_LOOKUP[prog_vfo]
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if mem.number < 999:
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flag.skip = chirp_common.SKIP_VALUES.index(mem.skip)
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